MEDIATEK Ralink MT7620 - Interrupt Controller

PGMT7620_V.1.0_040503
Page 53 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.4 Interrupt Controller
2.4.1 Features
 Supports a central point for interrupt aggregation for platform related blocks
 Separated interrupt enable and disable registers
 Supports global disable function
 2-level Interrupt priority selection
 Each interrupt source can be directed to IRQ#0 or IRQ#1
NOTE: MT7620 supports MIPS 24K’s vector interrupt mechanism.
There are 6 hardware interrupts supported by MIPS 24K. The interrupt allocation is shown below:
MIPS H/W interrupt pins
Connect to
Remark
HW_INT#5
Timer interrupt
Highest priority
HW_INT#4
Reserved
HW_INT#3
FE
HW_INT#2
PCIe
HW_INT#1
Other high priority interrupts (IRQ#1)
HW_INT#0
Other low priority interrupts (IRQ#0)
Lowest priority
2.4.2 Block Diagram
Interrupt
Masking
Interrupt Priority
Selection
PalmBus Interface
Interrupts
(from platform blocks)
PalmBus
(to/from MIPS)
MIPS
Interrupt Controller
MIPS Timer INT
IRQ1
(high priority)
IRQ0
(low priority)
INT 5
INT 4
INT 3
INT 2
INT 1
INT 0
Figure 2-3 Interrupt Controller Block Diagram