MEDIATEK Ralink MT7620 - Pdma R

PGMT7620_V.1.0_040503
Page 39 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
NOTE: For more information on pin sharing schemes, see the datasheet for this chip.
24. PCIPDMA_STAT: Control and Status of PDMA in PCIe Device (offset: 0x0064)
Bits
Type
Name
Description
Initial Value
31:4
-
-
Reserved
0x0
3
RW
PCIPDMA_RX_EN
PDMA Rx DMA Enable
In iNIC applications, the external Host can
enable the PDMA of a PCIe Device to start Rx
PDMA (from the point of view of the external
host).
However, the actual PDMA Rx is enabled when
both of following conditions are met.
 MIPS (internal CPU) writes 1 to
PCIPDMA_RX_EN.
 External Host writes 1 to RX_DMA_EN via
BAR1.
0x0
2
RW
PCIPDMA_TX_EN
PDMA Tx DMA Enable
In iNIC applications, the external Host can
enable the PDMA of a PCIe Device to start Tx
PDMA (from the point of view of the external
host).
However, the actual PDMA Tx is enabled when
both of following conditions are met.
 MIPS (internal CPU) writes 1 to
PCIPDMA_TX_EN.
 External Host writes 1 to TX_DMA_EN via
BAR1.
0x0
1
RO
PCIPDMA_RX_BUSY
PCIe PDMA Rx Busy
Indicates PDMA Rx in the PCIe device is busy.
0: PDMA Rx is idle
1: PDMA Rx is busy
0x0
0
RO
PCIPDMA_TX_BUSY
Indicates PDMA Tx in the PCIe device is busy.
0: PDMA Tx is idle
1: PDMA Tx is busy
0x0
25. PMU0_CFG: (offset: 0x0088)
Bits
Type
Name
Description
Initial Value
31:29
-
-
Reserved
0x0
28
RW
PMU_SW_SET
PMU Software Register Set
0: Set hardware to control the PMU software
register.
1: Set software to control the software register
field [24:16]
0x0
24
RW
A_DCDC_EN
SW Analog DC/DC Converter Enable
0: Disable
1: Enable
0x1