MEDIATEK Ralink MT7620 - Page 40

PGMT7620_V.1.0_040503
Page 40 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
23:20
-
-
Reserved
0x0
19
RW
A_SSCPERI
Analog Spread Spectrum Clock Generator
(SSCG) Modulation Period Select
0: 16.5 kHz
1: 33 kHz
0x1
18
RW
A_SSCGEN
Analog Spread Spectrum Clock Generator
Enable
0: Disable
1: Enable
0x1
17:16
RW
A_SSC
Analog Spread Spectrum Clock Control
Increases the SSCG modulation frequency from
a base level of 1 MHz.
<0x0>: ± 5%
<0x1>: Reserved
<0x2>: ± 10%
<0x3>: ± 20%
0x2
15:11
-
-
Reserved
0x0
10:8
RW
A_DLY
Analog Delay
Controls the output power MOSFET dead zone.
Sets the turn off/delay period between the
external upper and lower MOSFET. The periods
given below are approximate as the exact value
depends on the production process for each
chip, the input voltage, and the chip
temperature.
<0x1>: Approx. 40 nsec
<0x2>: Approx. 30 nsec
<0x3:> Approx. 20 nsec
<0x4:> Approx. 10 nsec
0x2
7:0
RW
A_VTUNE
Analog Voltage Tune
Sets the output voltage level.
<0x51>: 0.76 V (min)
…
<0xB9>: 1.75 V - 20 mv
<0xBA>: 1.75 V - 10 mv
<0xBB>: 1.75 V (default)
<0xBC>: 1.75 V + 10 mv
<0xBD>: 1.75 V + 20 mv
…
<0xFF> : 2.4 V (max)
0xBB
26. PMU1_CFG: (offset: 0x008C)
Bits
Type
Name
Description
Initial Value
31:30
-
-
Reserved
-