MEDIATEK Ralink MT7620 - Page 41

PGMT7620_V.1.0_040503
Page 41 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
29:28
RW
DIG_LDO_GAIN
DIG_LDO gain control
00: High DC gain
00: Reserved
10: Reserved
11: Low DC gain
0x0
27:26
-
-
Reserved
-
25
RW
DIG_SW_SEL
SW Configured Digital LDO output level
0: HW controlled DIG LDO
1: SW controlled DIG LDO field [24:16]
0x0
24
RW
DIG_LDO_EN
DIG LDO Enable
0: Disable
1: Enable
0x1
23:16
RW
DIG_LDO_VALUE
LDO Output Level Selection
0x69
15:14
-
-
Reserved
-
13:12
RW
DDR_LDO_Gain
DDR LDO gain control
00: High DC gain
00: Reserved
10: Reserved
11: Low DC gain
0x0
11:10
-
-
Reserved
-
9
RW
DDR_SW_SEL
SW Config DDR LDO Output Level
0: HW control DDR LDO (based on bootstrap
value)
1: SW control DDR LDO field [8:0]
0x0
8
RW
DDR_LDO_EN
DDR LDO Enable
0: Disable
1: Enable
0x1
7:0
RW
DDR_LDO_VALUE
LDO Output Level Selection
default:
<10011011> for output=1.8 V (DDR2)
<11010101> for output=2.5 V (DDR1)
BS
27. PPLL_CFG0: PCIe PLL Configuration 0 (offset: 0x0098)
Bits
Type
Name
Description
Initial Value
31
RW
PPLL_SW_SET
Progammable PLL Software Set
0: HW sets default PLL parameters
1: SW applies new parameters with
PPLL_CFG0[23:0] & PPLL_CFG1[9:0] &
PPLL_CFG1[26]
0x0
30:24
-
-
Reserved
0x0