MEDIATEK Ralink MT7620 - Register Descriptions ( Base: 0 X 1000_0 C00)

PGMT7620_V.1.0_040503
Page 74 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.7.4 Register Descriptions (base: 0x1000_0C00)
59. RBR: Receive Buffer Register (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RO
RXD
Receive Buffer Data
Data is transferred to this register from the Rx
shift register after a full character is received.
The OE bit in the LSR register is set if the
contents of this register have not been read
before another character is received, indicating
an Rx buffer overrun.
0x0
60. TBR: Transmit Buffer Register (offset: 0x0004)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RO
TXD
Transmit Buffer Data
When a character is written to this register, it is
stored in the Tx holding register; if the Tx
register is empty, the character is moved to the
Tx register, starting transmission.
0x0
61. IER: Interrupt Enable Register (offset: 0x0008)
Bits
Type
Name
Description
Initial Value
31:3
-
-
Reserved
0x0
2
RW
ELSI
Enable Line Status Interrupts
Enables the following Rx line status interrupts.
 Overrun Error (OE)
 Parity Error (PE)
 Framing Error (FE)
 Break Interrupt (BI)
0x0
1
RW
ETBEI
Enable Tx Buffer Empty Interrupt
Enables the Tx buffer empty interrupt (THRE),
which indicates the Tx buffer is empty.
0x0
0
RW
ERBFI
Enable Rx Buffer Full Interrupt
Enables the Rx buffer full interrupt, as well as
the Data Ready (DR) and Character Time-Out
interrupts.
0x0
NOTE:
0: Disable
1: Enable