MEDIATEK Ralink MT7620 - List of Registers

PGMT7620_V.1.0_040503
Page 154 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.14.4 List of Registers
No.
Offset
Register Name
Description
Page
191
0x0000
I2S_CFG
I
2
S Configuration
155
192
0x0004
INT_STATUS
Interrupt Status
156
193
0x0008
INT_EN
Interrupt Enable
156
194
0x000C
FF_STATUS
FIFO Status
157
195
0x0010
TX_FIFO_WREG
Transmit FIFO Write to Register
157
196
0x0014
RX_FIFO_RREG
Receive FIFO Read Register
157
197
0x0018
I2S_CFG1
I
2
S Configuration 1
157
198
0x0020
DIVCOMP_CFG
Integer Part of the Dividor Register 1
158
199
0x0024
DIVINT_CFG
Integer Part of the Dividor Register 2
158