MEDIATEK Ralink MT7620 - Register Descriptions ( Base: 0 X 1000_0100)

PGMT7620_V.1.0_040503
Page 49 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.3.4 Register Descriptions (base: 0x1000_0100)
30. TMRSTAT: Timer Status Register (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31:6
-
-
Reserved
0x0
5
WO
TMR1RST
Timer 1 Reset
Read
Reading this bit returns a 0.
Write
0: No effect.
1: Reset Timer 1 to 0xFFFF if in free-running
mode, or to the value specified in the
TMR1LOAD register in all other modes.
0x0
4
WO
TMR0RST
Timer 0 Reset
Read
Reading this bit returns a 0.
Write
0: No effect.
1: Reset Timer 0 to 0xFFFF if in free-running
mode, or to the value specified in the
TMR0LOAD register in all other modes.
0x0
3:2
-
-
Reserved
0x0
1
R/W1C
TMR1INT
Timer 1 Interrupt Status
Indicates that timer 1 has expired and timer 1
interrupt to the processor has asserted. After
the interrupt is sent, the bit is written to 1 and
cleared.
Read
0: Not asserted.
1: Asserted.
Write
0: No effect
1: Clears the interrupt.
0x0
0
R/W1C
TMR0INT
Timer 0 Interrupt Status
Indicates that timer 0 has expired and timer 0
interrupt to the processor has asserted. After
the interrupt is sent, the bit is written to 1 and
cleared.
Read
0: Not asserted.
1: Asserted.
Write
0: No effect
1: Clears the interrupt.
0x0