MEDIATEK Ralink MT7620 - Page 42

PGMT7620_V.1.0_040503
Page 42 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
23:22
RW
AFC_WAIT_TIME
Automatic Frequency Control (AFC) Wait Time
The time AFC waits until BIAS is ready.
00: 5 μs
01: 10 μs
10: 20 μs
11: 40 μs
0x0
21:20
RW
PLL_LOCK_TIME
PLL Lock Time
The time PLL starts to lock after AFC is ready.
00: 5 μs
01: 10 μs
10: 20 μs
11: 40 μs
0x0
19
RW
EC_PEPLLOK
PCIe PLL Lock OK
0: Check AFC. After AFC, if F
vco
is within ± 3.2%
of the target value, this bit is set to 1.
1: Set this bit to always indicate CPU Lock status
is OK, and disable the AFC check.
0x0
18:17
-
-
Reserved
0x0
16
RW
OPEN_LOOP
PLL Open Loop
Forces PLL to operate in open loop mode.
0: Close loop
1: Open loop
0x0
15
RW
LC_PERFCK
(Logic side Code) PCIe Reference Clock
Frequency Source
0: 40 MHz
1: 20 MHz
BS
14
RW
BYPASS_REF_CLK
Bypass Reference Clock
0: Normal
1: Bypass
0x0
13:12
RW
IPATH_INI_VAL
I-path Initial Voltage
00: Reserved
01: 500 mV
10: 600 mV (default)
11: 700 mV
0x2
11:10
RW
PLL_OUT_FREQ
Output Clock Frequency
00: 50 MHz (test only)
01: 100 MHz (default)
10: 200 MHz (test only)
11: 600 MHz (test only)
0x1