MEDIATEK Ralink MT7620 - Page 143

PGMT7620_V.1.0_040503
Page 143 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
4
RW
START
Start SPI Flash Transaction Mode
0: No effect
1: Starts SPI internal controller to start an SPI
instruction transaction.
NOTE: The BUSY bit in the SPISTAT register is
set when this bit is set and is cleared when the
data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.
0x0
3
RW
HIZSDO
Tri-state Data Out
0: The SPIDO pin remains driven after the cycle
is complete.
1: The SPIDO pin is tri-stated after the cycle is
complete.
NOTE: This bit applies to write transfers only;
for read transfers the SPIDO pin is tri-stated
during the transfer.
0x0
2
WO
STARTWR
Start SPI Write Transfer
0: No effect.
1: The contents of the SPIDATA register are
transferred to the SPI slave device.
NOTE: The BUSY bit in the SPISTAT register is
set when this bit is set and is cleared when the
data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.
0x0
1
WO
STARTRD
Start SPI Read Transfer
0: No effect.
1: Start a read from the SPI slave. The read data
is placed in the SPIDATA register.
NOTE: The BUSY bit in the SPISTAT register is
set when this bit is set and is cleared when the
data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.
0x0
0
RW
SPIENA
SPI Enable
0: The SPIENA pin is negated.
1: The SPIENA pin is asserted.
0x0
176. SPIDATA0: SPI Interface 0 Data (offset: 0x0020)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
-