MEDIATEK Ralink MT7620 - Page 144

PGMT7620_V.1.0_040503
Page 144 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
7:0
RW
SPIDATA
SPI Data Transfer
This register is used for command/data
transfers on the SPI interface. The use of this
register is given below:
Write
The bits to be transferred are written here,
including both command and data bits. If values
are transmitted MSB (most significant bit) first,
the command is placed in the upper bits and
the data in the lower bits. Bit 0 of the data is
written to SPIDATA [0]; bit 0 of the command
follows the MSB of the data. If data is
transmitted LSB (least significant bit) first, the
command is placed in the lower bits and the
data is placed in the upper bits.
Read
The command bits are written here. Bit 0 of the
command is written to SPIDATA[0]. When the
transfer is complete, the data transferred from
the slave may be read from the lower bits of
this register.
When using SPI Flash transaction, this
SPIDATA[7:0] is used for SPI_INSTR[7:0].
0x0
177. SPIADDR0: SPI Interface 0 Address (offset: 0x0024)
Bits
Type
Name
Description
Initial Value
31:0
RW
SPI_ADDR
SPI Flash Address
When 3-Byte SPI address is configured,
SPI_ADDR[31:8] is used.
When 4-Byte SPI address is configured,
SPI_ADDR[31:0] is used.
0x0
178. SPIBS0: SPI Interface 0 Block Size (offset: 0x0028)
Bits
Type
Name
Description
Initial Value
31:0
RW
SPI_BLOCKSIZE
SPI Block Size
Defines how many data bytes are transferred
during an SPI instruction execution.
0x0
179. SPIUSER0: SPI Interface 0 User Mode (offset: 0x002C)
Bits
Type
Name
Description
Initial Value
31:22
-
-
Reserved
0x0
21
RW
USERMODE
User Manual SPI Mode Enable
0: Disable user mode
1: Enable user mode. Allows SW to set the
phase and type of SPI commands that are
not pre-defined.
0x0