MEDIATEK Ralink MT7620 - Page 145

PGMT7620_V.1.0_040503
Page 145 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
20
RW
INSTR_PHASE
Instruction Phase
0: No instruction bytes
1: One byte instruction phase (SPIDATA0)
0x0
19:17
RW
ADDR_PHASE
Address Phase
000: No address byte
001: One byte address phase
(SPIADDR0[31:24])
010: Two byte address phase
(SPIADDR0[31:16])
011: Three byte address phase
(SPIADDR0[31:8])
100: Four byte address phase (SPIADDR0[31:0])
Others: Reserved
0x0
16
RW
MODE_PHASE
Mode Phase Byte Count
0: No mode bytes
1: One mode byte (SPIMD0[31:24])
0x0
15:14
RW
DUMMY_PHASE
Dummy Phase Byte Count
00: No dummy phase
01: One dummy byte
10: Two dummy bytes
11: Three dummy bytes
0x0
13:12
RW
DATA_PHASE
Data Phase Type
00: No data phase
01: Read data phase
10: Write data phase
11: Reserved
Data writes to Tx/Rx FIFO when user mode is
enabled.
0x0
11:9
RW
ADDR_TYPE
Address Transfer Type
001: Single Address Mode
010: Dual Address Mode
100: Quad Address Mode
Others: Reserved
0x0
8:6
RW
MODE_TYPE
Mode Transfer Type
001: Single Address Mode
010: Dual Address Mode
100: Quad Address Mode
Others: Reserved
0x0
5:3
RW
DUMMY_TYPE
Dummy Transfer Type
001: Single Address Mode
010: Dual Address Mode
100: Quad Address Mode
Others: Reserved
0x0