MEDIATEK Ralink MT7620 - Page 146

PGMT7620_V.1.0_040503
Page 146 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
2:0
RW
DATA_TYPE
Data Transfer Type
001: Single Address Mode
010: Dual Address Mode
100: Quad Address Mode
Others: Reserved
0x0
180. SPITXFIFO0: SPI Interface 0 TX_FIFO (offset: 0x0030)
Bits
Type
Name
Description
Initial Value
31:8
RW
TX_FIFO
This register is used to write
TX_DMA_FIFO[31:8].
0x0
7:0
RW
TX_FIFO
This register is used to write TX
FIFO[7:0]/TX_DMA_FIFO[7:0].
0x0
181. SPIRXFIFO0: SPI Interface 0 RX_FIFO (offset: 0x0034)
Bits
Type
Name
Description
Initial Value
31:8
RC
RX_FIFO
This register is used to read RX DMA FIFO[31:8].
0x0
7:0
RC
RX_FIFO
This register is used to read RX
FIFO[7:0]/RX_DMA_FIFO[7:0].
0x0
182. SPIFIFOSTAT0: SPI Interface 0 FIFO_STATUS (offset: 0x0038)
Bits
Type
Name
Description
Initial Value
31:20
-
-
Reserved
0x0
19
RO
TX_EMPTY
Tx FIFO Empty
0x1
18
RO
RX_EMPTY
Rx FIFO Empty
Should not read SPIRXFIFO0 data when this flag
is true.
0x1
17
RO
TX_FULL
Tx FIFO Full
Should not write SPITXFIFO0 data when this flag
is true.
0x0
16
RO
RX_FULL
Rx FIFO Full
0x0
15:8
RO
TX_FIFO_CNT
Tx FIFO Count
Transmit FIFO Depth = 16,
When TX_FIFO_CNT=0, TX_EMPTY=1.
When TX_FIFO_CNT=16, TX_FULL=1.
0x0
7:0
RO
RX_FIFO_CNT
Rx FIFO Count
Receive FIFO Depth = 16,
When RX_FIFO_CNT=0, RX_EMPTY=1.
When RX_FIFO_CNT=16, RX_FULL=1.
0x0
NOTE: Where applicable,
0: False
1: True