MEDIATEK Ralink MT7620 - Page 147

PGMT7620_V.1.0_040503
Page 147 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
183. SPIMD0: SPI Interface 0 Mode (offset: 0x003C)
Bits
Type
Name
Description
Initial Value
31:24
RW
SPI_MODE
SPI Flash Mode
Selects the SPI flash mode. Available modes
depend on the SPI flash vendor. For more
information on available modes, please check
the datasheet provided by the SPI vendor.
0x0
23:0
RW
SPI_DUMMY
SPI Dummy
Contains data used for dummy writes to the SPI
flash.
0x0
184. SPISTAT1: SPI Interface 1 Status (offset: 0x0040)
Bits
Type
Name
Description
Initial Value
31:2
-
-
Reserved
-
0
RO
BUSY
SPI Transfer In Progress
0: The SPI interface is inactive.
1: An SPI transfer is in progress.
NOTE: This bit must be 0 before initiating a
transfer. Any attempt to start a data transfer
will be ignored if this bit is 1.
0x0
185. SPICFG1: SPI Interface 1 Configuration (offset: 0x0050)
Bits
Type
Name
Description
Initial Value
31:12
-
-
Reserved
-
11
RW
RXENVDIS
Rx Pre-Envelope Disable
Disables setting a pre-data input before the first
data is received.
0: Enable clock PRE_ENVELOP when
(CLOCK_POL ^ RX_CLKEDGE = 0)
1: Disable clock PRE_ENVELOP (SPI flash mode)
0x0
10
RW
RXCAP
Rx Capture Delay Mode
0: Rx data captured is not delayed.
1: Rx data captured is delayed for half a SPICLK
cycle.
0x0
9
-
-
Reserved
-
8
RW
MSBFIRST
Bit Transfer Order
0: LSB bits of data sent/received first.
1: MSB bits of data sent/received first.
NOTE: This bit applies to both the command
and data.
0x1
7
-
-
Reserved
-