MEDIATEK Ralink MT7620 - Page 148

PGMT7620_V.1.0_040503
Page 148 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
6
RW
SPICLKPOL
SPI Clock Default Polarity
Sets the default state of the SPICLK.
0: Logic 0
1: Logic 1
NOTE: This bit is ignored if the SPI interface
block is a slave (SPISLAVE bit is set).
0x0
5
RW
RXCKEDGE
SPI Clock Default State
0: Data is captured on the rising edge of the
SPICLK signal.
1: Data is captured on the falling edge of the
SPICLK signal.
0x0
4
RW
TXCKEDGE
SPI Clock Default State
0: Data is transmitted on the rising edge of the
SPICLK signal.
1: Data is transmitted on the falling edge of the
SPICLK signal.
0x0
3
RW
HIZSPI
Tri-states all SPI pins
0: SPICLK and SPIENA pin are driven.
1: SPICLK and SPIENA pin are tri-stated.
NOTE: This bit overrides all normal
functionality.
0x0
2:0
RW
SPICLK
SPI Clock Divide Control
Sets the SPI clock divisor.
0: SPICLK rate = system clock rate/ 2
1: SPICLK rate = system clock rate / 4
2: SPICLK rate = system clock rate / 8
3: SPICLK rate = system clock rate / 16
4: SPICLK rate = system clock rate / 32
5: SPICLK rate = system clock rate / 64
6: SPICLK rate = system clock rate / 128
7: SPICLK is disabled
NOTE: These rates may change in the future.
0x4
186. SPICTL1: SPI Interface 1 Control (offset: 0x0054)
Bits
Type
Name
Description
Initial Value
31:4
-
-
Reserved
-
3
RW
HIZSDO
Tri-state Data Out
0: The SPIDO pin remains driven after the cycle
is complete.
1: The SPIDO pin is tri-stated after the cycle is
complete.
NOTE: This bit applies to write transfers only;
for read transfers the SPIDO pin is tri-stated
during the transfer.
0x0