MEDIATEK Ralink MT7620 - Page 149

PGMT7620_V.1.0_040503
Page 149 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
2
WO
STARTWR
Start SPI Write Transfer
0: No effect.
1: The contents of the SPIDATA register are
transferred to the SPI slave device.
NOTE: The BUSY bit in the SPISTAT register is
set when this bit is set and is cleared when the
data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.
0x0
1
WO
STARTRD
Start Read
0: No effect.
1: Start a read from the SPI slave. The read data
is placed in the SPIDATA register.
NOTE: The BUSY bit in the SPISTAT register is
set when a this bit is set and is cleared when
the data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.
0x0
0
RW
SPIENA
SPI Enable
0: The SPIENA pin is set low.
1: The SPIENA pin is set high.
0x0
187. SPIDATA1: SPI Interface 1 Data (offset: 0x0060)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
-
7:0
RW
SPIDATA
This register is used for command/data
transfers on the SPI interface. The use of this
register is given below:
Write
The bits to be transferred are written here,
including both command and data bits. If
values are transmitted MSB (most
significant bit) first, the command is placed in
the upper bits and the data in the lower bits.
Bit 0 of the data is written to SPIDATA
[0]; bit 0 of the command follows the MSB of
the data. If data is transmitted LSB (least
significant bit) first, the command is placed
in the lower bits and the data is placed in the
upper bits.
Read
The command bits are written here. Bit 0 of the
command is written to SPIDATA[0]. When the
transfer is complete, the data transferred from
the slave may be read from the lower bits of
this register.
0x0