MEDIATEK Ralink MT7620 - Page 150

PGMT7620_V.1.0_040503
Page 150 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
188. SPIDMA: SPI Interface DMA (offset: 0x0080)
Bits
Type
Name
Description
Initial Value
31:11
-
-
Reserved
0x0
10:9
RW
TxBurstSize
The number of transfers in a Tx burst
transaction.
‘b00: 1 transfer
‘b01: 2 transfers
‘b10: 4 transfers
Others: Undefined
0x1
8
RW
TXDMA
Tx DMA Enable
0: Disable Tx GDMA
1: Write Tx FIFO from GDMA
0x0
7:3
-
-
Reserved
0x0
2:1
RW
RxBurstSize
The number of transfers in a Rx burst
transaction.
‘b00: 1 transfer
‘b01: 2 transfers
‘b10: 4 transfers
Others: Undefined
0x1
0
RW
RXDMA
Rx DMA Enable
0: Disable Rx GDMA
1: Read Rx FIFO from GDMA
0x0
189. SPIDMASTAT: SPI Interface DMA FIFO Status (offset: 0x0084)
Bits
Type
Name
Description
Initial Value
31:20
-
-
Reserved
0x0
19
RO
TX_DMA_EMPTY
Indicates the Tx DMA FIFO is empty.
0x1
18
RO
RX_DMA_EMPTY
Indicates the Rx DMA FIFO is empty.
0x1
17
RO
TX_DMA_FULL
Indicates the Tx DMA FIFO is full.
0x0
16
RO
RX_DMA_FULL
Indicates the Rx DMA FIFO is full.
0x0
15:8
RO
TX_DMA_CNT
Shows the value of the Tx DMA FIFO counter.
0x0
7:0
RO
RX_DMA_CNT
Shows the value of the Rx DMA FIFO counter.
0x0
NOTE: Where applicable,
0: False
1: True
190. SPIARB: SPI Interface Arbiter (offset: 0x00F0)
Bits
Type
Name
Description
Initial Value
31
RW
ARB_EN
Arbiter Enable
0: Only one SPI interface will work depending
on CSCTL settings.
1: SPI Interface 0 and 1 work concurrently.
0x0
30:19
-
-
Reserved
-