MEDIATEK Ralink MT7620 - Page 151

PGMT7620_V.1.0_040503
Page 151 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
18:16
RW
CSCTL
Chip Select Control
000: SPI control for chip select 0
001: SPI control for chip select 1
010-111: Reserved
0x0
15:2
-
-
Reserved
-
1
RW
SPI1_POR
SPI1 Pin Polarity Read
Indicates that the SPI device on interface 1 is
active depending on whether the chip enable
pin is high or low.
0: Active when the chip enable pin is low.
1: Active when the chip enable pin is high.
0x0
0
RW
SPI0_POR
SPI0 Polarity Read
Indicates that the SPI device on interface 0 is
active depending on whether the chip enable
pin is high or low.
0: Active when the chip enable pin is low.
1: Active when the chip enable pin is high
0x0
NOTE: This register must be configured when SPI interface 1 is activated.