MEDIATEK Ralink MT7620 - Page 71

PGMT7620_V.1.0_040503
Page 71 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
57. DLLO: Clock Divider Divisor Latch Low (offset: 0x002C)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RW
DLLO
This register is the equivalent to the lower 8
bits of the DL register. It is provided for16550
compatibility.
NOTE: In standard 16550 implementation, this
register is accessible as two 8-bit halves only.
For convenience, the divisor latch is accessible
as a single 16-bit entity via the DL register.
0x1
58. DLHI: Clock Divider Divisor Latch High (offset: 0x0030)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RW
DLHI
This register is the equivalent to the upper 8
bits of the DL register. It is provided for 16550
compatibility.
NOTE: In standard 16550 implementation, this
register is accessible as two 8-bit halves only.
For convenience, the divisor latch is accessible
as a single 16-bit entity via the DL register.
0x0