MEDIATEK Ralink MT7620 - Page 70

PGMT7620_V.1.0_040503
Page 70 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
2
RC
TERI
Trailing Edge Ring Indicator
Indicates when the RIN (Ring Indicator) pin
changes from a low to a high value.
0x0
1
RC
DDSR
Delta Data Set Ready
Indicates when the DSRN (Data Set Ready) pin
changes.
0x0
0
RC
DCTS
Delta Clear to Send
Indicates when the CTSN (Clear to Send) pin
changes.
0x0
NOTE:
0: False
1: True
55. SCRATCH: Scratch Register (offset: 0x0024)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RW
SCRATCH
Scratch
This register is defined as a scratch register in
16550 application. It has no hardware function,
and is retained for compatibility only.
0x0
56. DL: Clock Divider Divisor Latch (offset: 0x0028)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
0x0
15:0
RW
DL
Divisor Latch
This register is used in the clock divider to
generate the baud clock.
The baud rate (transfer rate in bits per second)
is defined as:
baud rate = 40 MHz / (CLKDIV * 16).
0x1
NOTE:
1. In standard 16550 implementation, this register is accessible as two 8-bit halves only. In this implementation,
the DL register is accessible as a single 16-bit entity only.
2. DL[15:0] should be >= 4.
SRC Clock Freq.
Req. Baud Rate (Bd)
DL [15:0]
Err Rate (%)
40 MHz
57000
44
-0.32%
115200
22
-1.36%
230400
11
-1.36%
345600
7
3.34%
460800
5
8.51%