MEDIATEK Ralink MT7620 - Page 100

PGMT7620_V.1.0_040503
Page 100 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
15:0
RW
CLKDIV
Clock Divisor
The value written to this register is used to
generate the I2C bus SCLK signal by applying
the following equation:
SCLK frequency = 40 MHz / ( 2 x CLKDIV )
NOTE:
1. Only values of 8 and above are valid.
2. Due to synchronization between the I
2
C
internal clock and the system clock, the exact
equation is actually
SCLK frequency = PB_CLK frequency / ((2 x
CLKDIV) + 5).
For most systems, CLKDIV is usually
programmed to very larger numbers since the
system clock frequency should be orders of
magnitude faster than the I2C bus clock. These
results in the synchronization errors being
insignificant and the exact equation
approximating the simpler one given above.
0x0
113. DEVADDR: I
2
C Device Address Register (offset: 0x0008)
Bits
Type
Name
Description
Initial Value
31:7
-
-
Reserved
0x0
6:0
RW
DEVADDR
I
2
C Device Address
This value is transmitted as the device address,
if DEVADDIS bit in the CONFIG register is not set
to 1.
0x0
114. ADDR: I
2
C Address Register (offset: 0x000C)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RW
ADDR
I
2
C Address
These bits store the 8-bits of address to be sent
to the external I2C slave devices when the
ADDRDIS bit is 0.
0x0
115. DATAOUT: I
2
C Data Out Register (offset: 0x0010)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RW
DATAOU
I
2
C Data Out
These bits store the 8-bits of data to be written
to the external I2C slave devices during a write
transfer.
0x0