MEDIATEK Ralink MT7620 - Page 85

PGMT7620_V.1.0_040503
Page 85 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
73. GPIO23_00_RMASK: PIO Pin Rising Edge Interrupt Mask (offset: 0x0008)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
-
23:0
RW
PIORMASK
PIO Pin Rising Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
0 to a 1, i.e. a rising edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.
0x0
74. GPIO23_00_MASK: PIO Pin Falling Edge Interrupt Mask (offset: 0x000C)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
-
23:0
RW
PIOFMASK
PIO Pin Falling Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
1 to a 0, i.e. a falling edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.
0x0
75. GPIO23_00_DATA: PIO Pin Data (offset: 0x0020)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
-
23:0
RW
PIODATA
PIO Pin Data
These bits are used for driving or sensing static
signals on the PIO pins. To drive a value onto a
PIO pin, the corresponding bit in the PIODIR
register must be set. If the corresponding
direction bit is set, the value written to the bit
in the PIODATA register will be driven at the
pin. A read of this register returns the value of
the signals currently on the PIO pins.
NOTE:
1. The value of any bit in this register is inverted
with respect to the pin if the corresponding bit
in the PIOPOL register is set, both in input and
output modes.
2. The values read from the PIO pins are not
synchronized; the user should be sure that the
data will not change when this register is read,
or should be aware that the bits which are not
static at that time may be inaccurate.
PC