MEDIATEK Ralink MT7620 - Page 56

PGMT7620_V.1.0_040503
Page 56 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
14
RO
SDHC
SDHC interrupt after mask
0x0
13
-
-
Reserved
0x0
12
RO
UARTLITE
UARTLITE interrupt status after mask
0x0
11
RO
SPI
SPI interrupt status after mask
0x0
10
RO
I2S
I2S interrupt status after mask
0x0
9
RO
PC
MIPS performance counter interrupt status
after mask
0x0
8
-
-
Reserved
0x0
7
RO
DMA
DMA interrupt status after mask
0x0
6
RO
PIO
PIO interrupt status after mask
0x0
5
RO
UART
UART interrupt status after mask
0x0
4
RO
PCM
PCM interrupt status after mask
0x0
3
RO
ILL_ACC
Illegal access interrupt status after mask
0x0
2
RO
WDTIMER
Watchdog timer interrupt status after mask
0x0
1
RO
TIMER0
Timer 0 interrupt status after mask
0x0
0
RO
SYSCTL
System control interrupt status after mask
0x0
NOTE: These bits are set if the corresponding interrupt is asserted from the source and with the following two
conditions:
1. The interrupt is not masked (the bit is not set in the INTDIS register)
2. The interrupt type is set to INT1 (in the INTTYPE register).
NOTE: Writing to these bits is ignored and each bit cannot be simultaneously active in both the IRQ0STAT and
IRQ1STAT registers.
39. INTTYPE: Interrupt Type (offset: 0x0020)
Bits
Type
Name
Description
Initial Value
31:20
-
-
Reserved
-
19
RW
UDEV
USB device interrupt status type
0x0
18
RW
UHST
USB host interrupt status type
0x0
17
RW
ESW
Ethernet Switch interrupt status type
0x0
16
-
-
Reserved
0x0
15
RW
R2P
R2P Interrupt status type
0x0
14
RW
SDHC
SDHC Engine interrupt status type
0x0
13
-
-
Reserved
0x0
12
RW
UARTLITE
UARTLITE interrupt status type
0x0
11
RW
SPI
SPI interrupt status type
0x0
10
RW
I2S
I2S interrupt status type
0x0
9
RW
PC
MIPS performance counter interrupt status
type
0x0
8
-
-
Reserved
0x0
7
RW
DMA
DMA interrupt status type
0x0