MEDIATEK Ralink MT7620 - Page 288

PGMT7620_V.1.0_040503
Page 288 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
23:12
RW
VID5
VLAN Identifier for VLAN Table Index 5
0x006
11:0
RW
VID4
VLAN Identifier for VLAN Table Index 4
0x005
333. VTIM4: VID to Table Index Map 4 Register (offset: 0x010C)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
0x0
23:12
RW
VID7
VLAN Identifier for VLAN Table Index 7
0x008
11:0
RW
VID6
VLAN Identifier for VLAN Table Index 6
0x007
334. VTIM5: VID to Table Index Map 5 Register (offset: 0x0110)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
0x0
23:12
RW
VID9
VLAN Identifier for VLAN Table Index 9
0x00A
11:0
RW
VID8
VLAN Identifier for VLAN Table Index 8
0x009
335. VTIM6: VID to Table Index Map 6 Register (offset: 0x0114)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
0x0
23:12
RW
VID11
VLAN Identifier for VLAN Table Index 11
0x00C
11:0
RW
VID10
VLAN Identifier for VLAN Table Index 10
0x00B
336. VTIM7: VID to Table Index Map 7 Register (offset: 0x0118)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
0x0
23:12
RW
VID13
VLAN Identifier for VLAN Table Index 13
0x00E
11:0
RW
VID12
VLAN Identifier for VLAN Table Index 12
0x00D
337. VTIM8: VID to Table Index Map 8 Register (offset: 0x011C)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
0x0
23:12
RW
VID15
VLAN Identifier for VLAN Table Index 15
0x010
11:0
RW
VID14
VLAN Identifier for VLAN Table Index 14
0x00F
338. DBGC: Debug Control Register (offset: 0x0200)
Bits
Type
Name
Description
Initial Value
31
W1C
DBG_BUSY
Debug Mode Is Busy
SW can set this bit to 1 only if this bit is reset.
After DBGD1 and DBGD2 registers have been
written and this bit is set, this chip will perform
debug commands on the corresponding debug
control and data which reside in different
blocks based on DEBUG_ID.
0x0