MEDIATEK Ralink MT7620 - Page 112

PGMT7620_V.1.0_040503
Page 112 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
1
RO
DEC_ERR
Decode Error
Shows the ECC decode check status.
0: No error
1: Correctable error or ECC error
0x0
0
RO
BUSY
NAND flash controller is busy.
0: Idle
1: Busy
0x0
128. INT_ENA: Interrupt Enable (offset: 0x0034)
Bits
Type
Name
Description
Initial Value
31:17
-
-
Reserved
0x0
7:0
RW
INT_ENA
Interrupt Enable Control
0: Disable
1: Enable
0x0
129. INT_STA: Interrupt Status (offset: 0x0038)
Bits
Type
Name
Description
Initial Value
31:17
-
-
Reserved
0x0
7
W1C
RX_BUF_ERR1
Rx Buffer Error 1 Interrupt
Asserts when kicking a new transfer but the Rx
buffer is not empty.
0x0
6
W1C
TX_BUF_ERR1
Tx Buffer Error 1 Interrupt
Asserts when kicking a new transfer but the Tx
buffer is not empty.
0x0
5
W1C
RX_BUF_ERR0
Rx Buffer Error 0 Interrupt
Asserts when transfer is complete but the Rx
buffer is not empty.
0x0
4
W1C
TX_BUF_ERR0
Tx Buffer Error 0 Interrupt
Asserts when transfer is compete but the Tx
buffer is not empty.
0x0
3
W1C
ECC_ERR
ECC Check Error Interrupt
Asserts when an ECC error is detected.
0x0
2
W1C
RX_BUF_RRDY
Rx Buffer Read Ready Interrupt
Asserts when the Rx buffer is ready for reads.
0x0
1
W1C
TX_BUF_WRDY
Tx Buffer Write Ready Interrupt
Asserts when the Tx buffer is ready for writes.
0x0
0
W1C
XFER_DONE
Transfer Done Interrupt
Asserts when transfer is complete.
0x0
130. CTRL1: Control 1 (offset: 0x003C)
Bits
Type
Name
Description
Initial Value
31:20
-
-
Reserved
0x0
19:16
RW
ECC_BYTE3_LOC
The location of 3
rd
ECC byte in spare 16-byte
0x8