MEDIATEK Ralink MT7620 - Page 128

PGMT7620_V.1.0_040503
Page 128 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
26
RO
TXD_GLT_ST
TXD Glitch Status
Indicates if a glitch is detected in a TXD signal. It
can be cleared by bit[31].
0: Not detected.
1: Detected
0x0
25:23
-
-
Reserved
0x0
22
RO
CHENN_GLT_ST
CHEN Negative Glitch Status
Indicates if a glitch is detected in a CHEN signal.
It can be cleared by bit[30] (negedge sample).
0: Not detected.
1: Detected
0x0
21:19
-
-
Reserved
0x0
18
RO
CHENP_GLT_ST
CHEN Positive Glitch Status
Indicates if a glitch is detected in a CHEN signal.
It can be cleared by bit[30] (posedge sample).
0: Not detected.
1: Detected
0x0
17
-
-
Reserved
0x0
16
RO
CHENPD_GLT_ST
CHEN Positive Delay Glitch Status
Indicates if a glitch is detected in a CHEN signal.
It can be cleared by bit[30] (posedge sample,
delay 1 cycle).
0: Not detected.
1: Detected
0x0
15
RW
TXD_DIGDLY_EN
TXD Digital Delay Enable
Enables digital delay path.
0: Disable
1: Enable
0x0
14:13
-
-
Reserved
0x0
12:8
RW
TXD_DLYVAL
Delay Count Value
The description is the same as the
CHEN_DLYVAL field in this register.
0x2
7
RW
CHEN_DIGDLY_EN
CHEN Digital Delay Enable
Enables the digital delay path.
0: Disable
1: Enable
0x0
6:5
-
-
Reserved
0x0