MEDIATEK Ralink MT7620 - Page 20

PGMT7620_V.1.0_040503
Page 20 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
8
RO
DRAM_FROM_EE
DRAM Configuration from EEPROM
0: DRAM/PLL configuration from EEPROM.
1: DRAM configuration from Auto Detect.
For more information see the Bootstrapping
Pins Description in the datasheet for this chip.
BS
7
RO
DBG_JTAG_MODE
Debug JTAG Mode
0: EPHY_LED
1: JTAG MODE
BS
6
RO
XTAL_FREQ_SEL
Xtal Frequency Select
0: 20 MHz
1: 40 MHz
BS
5:4
RO
DRAM_TYPE
DRAM Type
0: SDRAM (150 MHz) (LVTTL 3.3 V) TSOP
Package
1: DDR1 (200 MHz) TSOP Package
2: DDR2 (200 MHz) FBGA Package
BS
3:0
RO
CHIP_MODE
Chip Mode
A vector to set chip function/test/debug modes
in non-test/debug operation.
For more information see the Bootstrapping
Pins Description in the datasheet for this chip.
BS
5. SYSCFG1: System Configuration Register 0 (offset: 0x0014)
Bits
Type
Name
Description
Initial Value
31:30
-
-
Reserved
-
29:28
RW
DDR_DPIN_RXPWD
SDRAM Data Pin Receiver Circuit Power Down
Control*
(DQ/DQS)
0: Disable (SDR/DDR1/DDR2 default)
1: Enable
2: Enable while data pin is output mode.
3: Enable while data pin is input mode.
BS
27:26
RW
DDR_DPIN_ODT
SDRAM Data Pin On Die Termination Setting*
(DQ/DQS)
[27:26]
SDR
(3.3 V)
SDR
(2.5 V/
1.8 V)
DDR1
DDR2
0
(Disable)
(Disable)
(Disable)
(Disable)
1
75 Ω
75 Ω
75 Ω
75 Ω
2
150 Ω
150 Ω
150 Ω
150 Ω
3
N/A
N/A
N/A
N/A
BS