MEDIATEK Ralink MT7620 - Page 203

PGMT7620_V.1.0_040503
Page 203 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.19.4 Block Diagram
PPE
(Packet Processing Engine)
CDM
PDMA
Embedded Switch (2 GE + 4 FE ports)
TSO /CSO
Scatter/Gathering
DMA
Packet Switch
Fabric
CPU port (Port #0)
Ethernet PHY (5 FE EPHY)
P0 P1 P2 P3
P5 P4
5 x RJ45
RBus
RBus
SoC High-Speed Bus
SoC Peripheral Bus
PBus
GDM
PSE
Rx Checksum /
Shaper
PBus
Page Switch Fabric
PSE
GDM (w/. PCI supported)
PCI device
FOE entry
P6P7
Figure 2-25 Frame Engine Block Diagram