MEDIATEK Ralink MT7620 - Page 209

PGMT7620_V.1.0_040503
Page 209 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.19.8 Global Registers (base: 0x1010_0000)
2.19.8.1 List of Registers
No.
Offset
Register Name
Description
Page
241
0x0000
FE_GLO_CFG
Frame Engine Global Configuration
210
242
0x0004
FE_RST_GLO
Frame Engine Global Reset
210
243
0x0008
FE_INT_STATUS
Frame Engine Interrupt Status
210
244
0x000C
FE_INT_ENABLE
Frame Engine Interrupt Enable
212
245
0x0010
FOE_TS_T
Frame Offload Engine Time Stamp
213
246
0x0014
IPV6_EXT
IPv6 Extension Header
214
247
0x0018
G2P_FC
GSW to PDMA Flow Control
214
248
0x001C
P2G_FC
PDMA to GSW Flow Control
215