MEDIATEK Ralink MT7620 - Page 223

PGMT7620_V.1.0_040503
Page 223 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.19.10 PDMA Registers (base: 0x1010_0800)
2.19.10.1 List of Registers
No.
Offset
Register Name
Description
Page
271
0x0000, 0x0010,
0x0020, 0x0030
TX_BASE_PTRn
Tx Ring n Base Address Pointer
224
272
0x0004, 0x0014,
0x0024, 0x0034
TX_MAX_CNTn
Tx Ring n Maximum Count
224
273
0x0008, 0x0018,
0x0028, 0x0038
TX_CTX_IDXn
Tx Ring n CPU Transmit Index
224
274
0x000C, 0x001C,
0x002C, 0x003C
TX_DTX_IDXn
Tx Ring n DMA Transmit Index
224
275
0x0100, 0x0110
RX_BASE_PTRn
Rx Ring n Base Address Pointer
224
276
0x0104, 0x0114
RX_MAX_CNTn
Rx Ring n Maximum Count
224
277
0x0108, 0x0118
RX_CALC_IDXn
Rx Ring n CPU Allocate Index
224
278
0x010C, 0x011C
RX_DRX_IDXn
Rx Ring n DMA Receive Index
225
279
0x0200
PDMA_INFO
PDMA Information
225
280
0x0204
PDMA_GLO_CFG
PDMA Global Configuration
225
281
0x0208
PDMA_RST_IDX
PDMA Reset Index
226
282
0x020C
DELAY_INT_CFG
Delay Interrupt Configuration
227
283
0x0210
FREEQ_THRES
Free Queue Threshold
228
284
0x0220
INT_STATUS
Interrupt Status
228
285
0x0228
INT_MASK
Interrupt Mask
229
286
0x0280
SCH_Q01_CFG
Scheduler Configuration for Queue 0, 1
230
287
0x0284
SCH_Q23_CFG
Scheduler Configuration for Queue 2, 3
232