MEDIATEK Ralink MT7620 - Page 280

PGMT7620_V.1.0_040503
Page 280 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
22:20
RO
SA_PORT_FW
Source Address Hit Frame Port Forwarding
0x0
19
RO
SA_MIR_EN
Source Address Hit to Mirror Port
0x0
18:16
RO
USER_PRI
User Priority
0x0
15:13
RO
EG_TAG
Egress VLAN Tag Attribute
0x0
12
RO
LEAKY_EN
Leaky VLAN Enable
0x0
11:4
RO
PORT
Destination Port Map
0x0
3:2
RO
STATUS
Address Entry Live Status
0x0
1:0
RO
TYPE
Address Entry Type
0x0
Table 2-11 Address Table Read Data Register: DIP Entry
Bits
Type
Name
Description
Initial Value
31:19
-
-
Reserved
0x0
18:16
RO
USER_PRI
User Priority
0x0
15:13
RO
EG_TAG
Egress VLAN Tag Attribute
0x0
12
RO
LEAKY_EN
Leaky VLAN Enable
0x0
11:4
RO
PORT
Destination Port Map
0x0
3:2
RO
STATUS
Address Entry Live Status
0x0
1:0
RO
TYPE
Address Entry Type
0x0
Table 2-12 Address Table Read Data Register: SIP Entry
Bits
Type
Name
Description
Initial Value
31:12
-
-
Reserved
0x0
11:4
RO
PORT
Destination Port Map
0x0
3:2
RO
STATUS
Address Entry Live Status
0x0
1:0
RO
TYPE
Address Entry Type
0x0
324. VTCR: VLAN Table Control Register (offset: 0x0090)
Bits
Type
Name
Description
Initial Value
31
W1C
BUSY
VLAN Table Is Busy
SW can set this bit to 1 only if this bit is reset.
After the VTCR register is written and this bit is
set, this chip will perform the corresponding
function on the VLAN table based on FUNC bits.
0x0
30:17
-
-
Reserved
0x0
16
RO
IDX_INVLD
Entry is not Valid
This index for the access control is out of the
valid index.
0x0