MEDIATEK Ralink MT7620 - Page 283

PGMT7620_V.1.0_040503
Page 283 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
6:4
RW
PRI_USER
User Priority from ACL
0x0
3
RW
MIR_EN
Frame Copy to Mirror Port
0x0
2:0
RW
PORT_FW
Frame TO_CPU Forwarding
0x0
NOTE: For more information on this register, see the ACL Rule Control section.
Table 2-18 VLAN and ACL Write Data-I Register: trTCM Meter Table
Bits
Type
Name
Description
Initial Value
31
RW
CBS
Committed Burst Size
0x0
15:0
RW
PBS
Peak Burst Rate
0x0
326. VAWD2: VLAN and ACL Write Data-II Register (offset: 0x0098)
Table 2-19 VLAN and ACL Write Data-II Register: VLAN Entry
Bits
Type
Name
Description
Initial Value
31:16
RW
S_TAG2
Service Tag II
0x0
15:14
-
-
Reserved
0x0
13:12
RW
P6_TAG
P6 Egress Tag Control
0x0
11:10
RW
P5_TAG
P5 Egress Tag Control
0x0
9:8
RW
P4_TAG
P4 Egress Tag Control
0x0
7:6
RW
P3_TAG
P3 Egress Tag Control
0x0
5:4
RW
P2_TAG
P2 Egress Tag Control
0x0
3:2
RW
P1_TAG
P1 Egress Tag Control
0x0
1:0
RW
P0_TAG
P0 Egress Tag Control
0x0
Table 2-20 VLAN and ACL Write Data-II Register: ACL Rule Table
Bits
Type
Name
Description
Initial Value
31:20
-
-
Reserved
0x0
19
RW
EN
ACL Pattern Enable
0x0
18:16
RW
OFST_TP
Offset Range
0x0
15:8
RW
SP
Incoming Source Port Bit-map
0x0
7:1
RW
WORD_OFST
Word Offset
0x0
0
RW
CMP_SEL
Comparison mode selection
0x0
Table 2-21 VLAN and ACL Write Data-II Register: ACL Rule Mask
Bits
Type
Name
Description
Initial Value
31:0
RW
ACL_MASK
ACL Mask[63:32]
0x0
Table 2-22 VLAN and ACL Write Data-II Register: ACL Rate Control
Bits
Type
Name
Description
Initial Value
31:0
-
-
Reserved
0x0
Table 2-23 VLAN and ACL Write Data-II Register: ACL Rule Control