MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.20.8.2 Register Descriptions
342. MMSCR0_Q0Pn: Max-Min Scheduler Control Register 0 of Queue 0/Port n (offset: 0x1000, 0x1100,
0x1200, 0x1300, 0x1400, 0x1500, 0x1600, 0x1700)
Port n Queue x Minimum Traffic Arbitration
Scheme
1'b0: Round-Robin (RR)
1'b1: Strict Priority (SP)
Port n Queue x Minimum Rate Control Enable
1’b0: Disable queue 0 min. rate limit control.
When disabled, the shaper always lets
packets pass. (infinite rate)
1'b1: Enable queue 0 min. rate limit control.
Final Rate Limit = MAN*10^(EXP)*1 Kbps
where,
EXP: Rate Limit Exponent (defined in bit[11:8]
of this register)
MAN: Rate Limit Mantissa (defined in bit[6:0] of
this register)
Exponent part of Port n Queue x Min. Shaper
Rate Limit Control
Value range: 0 to 4
‘d0: 1 Kbps
‘d1: 10 Kbps
‘d2: 100 Kbps
‘d3: 1 Mbps
‘d4: 10 Mbps
Mantissa part of Port n Queue x Min. Shaper
Rate Limit Control
Value range: 1 to 100
343. MMSCR1_Q0Pn: Max-Min Scheduler Control Register 1 of Queue 0/Port n (offset: 0x1004, 0x1104,
0x1204, 0x1304, 0x1404, 0x1504, 0x1604, 0x1704)
Port n Queue x Maximum Traffic Arbitration
Scheme
1'b0: Weighted Fair Queuing (WFQ)
1'b1: Strict Priority (SP)
Port n Queue x Weighted Value For Maximum
WFQ
Weighted value = MAX_WEIGHT_Qx_Pn + 1