MEDIATEK Ralink MT7620 - Page 51

PGMT7620_V.1.0_040503
Page 51 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
3:0
RW
PRESCALE
Timer Clock Pre-scale
These bits are used to scale the timer clock in
order to achieve higher resolution or longer
timer periods. Their definitions are below.
Value
Timer Clock Frequency
0
System clock
1
System clock / 4
2
System clock / 8
3
System clock / 16
…
…
14
System clock / 32768
15
System clock / 65536
NOTE: The pre-scale value should not be
changed unless the timer is disabled.
0x0
34. TMR1LOAD: Timer 1 Load Value (offset: 0x0020)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
0x0
15:0
RW
TMRLOAD
Timer Load Value
This register contains the load value for the
timer. In all modes, this value is loaded into the
timer counter when this register is written. In
all modes except free-running mode, this value
is reloaded into the timer counter after the
timer counter reaches 0. It may be updated at
any time; the new value will be written to the
counter immediately.
0: Disable the timer, except in free-running
mode.
0x0
35. TMR1VAL: Timer 1 Counter Value (offset: 0x0024)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
0x0
15:0
RO
TMRVAL
Timer Counter Value
This register contains the current value of the
timer. During functional operation, writes have
no effect.
0xffff
36. TMR1CTL: Timer 1 Control (offset: 0x0028)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
0x0
15
RW
TESTEN
Test Enable
Reserved for testing. This bit should be set to 0.
0x0