MEDIATEK Ralink MT7620 - Page 68

PGMT7620_V.1.0_040503
Page 68 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
4
RW
LOOP
Loopback Mode Enable
0: Normal Operation.
1: The UART is put into loopback mode, and
used for self-testiing. The TXD pin is driven
high; the TXD signal connections are made
internally.
Signal
Wrapped Back Through:
TXD
RXD
DTRN
DSRN
RTSN
CTSN
OUT1N
RIN
OUT2N
DCDN
0x0
3
RW
OUT2
OUT2 Pin Value
0: OUT2N pin is driven to a high level.
1: OUT2N pin is driven to a low level.
NOTE: This bit is only functional in loopback
mode.
0x0
2
RW
OUT1
OUT1 Pin Value
0: OUT1N pin is driven to a high level.
1: OUT1N pin is driven to a low level.
NOTE: This bit is only functional in loopback
mode.
0x0
1
RW
RTS
RTSN1 Pin Value
0: RTSN pin is driven to a high level.
1: RTSN pin is driven to a low level.
0x0
0
RW
DTR
DTRN 1 Pin Value
0: DTRN pin is driven to a high level.
1: DTRN pin is driven to a low level.
0x0
53. LSR: Line Status Register (offset: 0x001C)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7
RC
ERINFIFO
Error in FIFO
Indicates that a FIFO contains data which was
received with a parity error, framing error, or
break condition.
0x0
6
RC
TEMT
Transmit Shift Register Empty
Indicates that the transmit shift register is
empty. This bit is reset when data is written to
the transmit buffer register (TBR).
0x1
5
RC
THRE
Transmit Holding Register Empty
Indicates that the transmitter holding register is
empty. This bit is reset when data is written to
the transmit buffer register (TBR).
0x1