MEDIATEK Ralink MT7620 - Page 88

PGMT7620_V.1.0_040503
Page 88 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
15:0
RC
PIOEDGE
The PIOEDGE bits have different meanings
depending on whether the interrupt for that
pin is enabled via the PIORMASK or PIOFMASK
register.
Read
If the PIO Pin Interrupt for this PIO pin is
asserted, the corresponding PIOEDGE bit
indicates whether a falling or rising edge
triggered the interrupt.
0: Interrupt triggered by falling edge.
1: Interrupt triggered by rising edge.
If the interrupt is masked (disabled), the
PIOEDGE bit is set on either a rising or falling
edge and remains set until cleared by firmware.
Bits corresponding to pins that are not set as
inputs will never be set.
Write
All bits are cleared by writing 1 to either this
register or the PIOINT register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.
0x0
83. GPIO39_24_RMASK: PIO Pin Rising Edge Interrupt Mask (offset: 0x0040)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
-
15:0
RW
PIORMASK
PIO Pin Rising Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
0 to a 1, i.e. a rising edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.
0x0
84. GPIO39_ 24_FMASK: PIO Pin Falling Edge Interrupt Mask (offset: 0x0044)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
-
15:0
RW
PIOFMASK
PIO Pin Falling Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
1 to a 0, i.e. a falling edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.
0x0