MEDIATEK Ralink MT7620 - Page 93

PGMT7620_V.1.0_040503
Page 93 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
98. GPIO71_40_SET: Set PIO Pin Data Bit (offset: 0x007C)
Bits
Type
Name
Description
Initial Value
31:0
RC
PIOSET
PIO Pin Set
Sets the corresponding bit in the PIODATA
output register.
0: No effect.
1: Set the selected PIODATA bit.
0x0
99. GPIO71_40_RESET: Clear PIO Pin Data bit (offset: 0x0080)
Bits
Type
Name
Description
Initial Value
31:0
RC
PIORESET
PIO Pin Reset
Clears the corresponding bit in the PIODATA
output register.
0: No effect.
1: Clear the selected PIODATA bit.
0x0
100. GPIO71_40_TOG: Toggle PIO Pin Data bit (offset: 0x0084)
Bits
Type
Name
Description
Initial Value
31:0
RC
PIOTOG
PIO Pin Toggle
Toggles the corresponding bit in the PIODATA
output register.
0: No effect.
1: Invert the selected PIODATA bit.
0x0
101. GPIO72_INT: PIO Pin Interrupt Status (offset: 0x0088)
Bits
Type
Name
Description
Initial Value
31:1
-
-
Reserved
-
0
RC
PIOINT
PIO Pin Interrupt
A PIOINT bit is set when its corresponding PIO
pin changes value and the edge for that pin is
enabled via the PIORMASK or PIOFMASK
register. The pin must be set as an input in the
PIODIR register to generate an interrupt.
Read
0: No change detected.
1: Change detected.
Write
All bits are cleared by writing 1 to either this
register or the PIOEDGE register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.
0x0
102. GPIO72_EDGE: PIO Pin Edge Status (offset: 0x008C)
Bits
Type
Name
Description
Initial Value
31:1
-
-
Reserved
-