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Panasonic FP0H - Page 153

Panasonic FP0H
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10.3 High-speed Counter Instruction
10-13
Example of program
The following example shows the program for setting the output Y0 when the elapsed value of
the high-speed counter CH0 matches K10000.
R0
K10000H0
F166 HC1S
Y0
DF
Precautions during programming
The high-speed counter control flag turns on until the value matches the target value after
the execution condition of the instruction has turned on. During this processing, the high-
speed counter instruction F165 (CAM0)/F166 (HC1S)/F167 (HC1R) cannot be executed for
the high-speed counter of the same channel.
When the hardware reset is performed before the elapsed value matches the target value,
the elapsed value will be reset. However, the settings of the target value and the target value
match output will not be cleared.
For the output Y specified for the target value match output, it is not checked whether the
output is overlapped with the OT, KP and other high-level instructions.
When describing the same channel in both the normal program and the interrupt program,
be sure to program not to execute them simultaneously.
REFERENCE
For details of the allocations of I/O and flags, refer to "12.2.4 When Using
High-speed Counter Function".
For details of the FPΣ mode, refer to "11. FPΣ Mode".

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