Panasonic FP0H - Page 164

High-speed Counter Function
10-24
10.4.3 Sample Program (Upper Limit Control, Instruction Clear, Addition)
The following shows the program for performing two cam outputs (R100, R101) according to
the elapsed value of the high-speed counter CH0. In the case of addition, when the elapsed
value reaches the target value (ON set value), the cam output turns on, and when it reaches
the target value (OFF set value), it turns off. When it reaches the target value (ON set value),
the interrupt program is started. When the elapsed value exceeds the upper limit, it returns to
0. The instruction is cleared by the high-speed counter control instruction F0 (MV).
Code
Value
Description
ⓐ
Positive maximum
value
When the instruction clear is executed, the upper limit control is canceled and
the counting continues up to the positive maximum value.
ⓑ
Upper limit When the elapsed value exceeds the upper limit, it returns to 0.
ⓒ
Target value 2: OFF
set value
The cam output is performed according to the target values.
In this example, the ON set value is smaller than the OFF set value for each
target value. Therefore,
When added: When the elapsed value reaches the ON set value, the cam
output turns on, and when it reaches the OFF set value, it turns off.
When subtracted: When the elapsed value falls below the OFF set value, the
cam output turns on, and when it falls below the ON set value, it turns off.
ⓓ
Target value 2: ON
set value
ⓔ
Target value 1: OFF
set value
ⓕ
Target value 1: ON
set value
①
Execution condition
When the execution condition turns on from off, the instruction is executed
and the cam control starts.
②
High-speed counter
instruction active flag
The high-speed counter instruction active flag turns on during the execution of
the instruction. When the high-speed counter control instruction F0 (MV) is
executed, it turns off.
③
Cam output The output turns ON/OFF according the set values.
④
Interrupt
In the case of addition, when the elapsed value reaches the ON set value, the
interrupt program is started.
⑤
Clear high-speed
counter instruction
By the high-speed counter control instruction F0 (MV), when the bit 3 of the
special data register DT90052 turns on from off, the executed F165 (CAM0)
instruction is cleared.