A-D Converter
M30240 Group
Rev.1.00 Sep 24, 2003 Page 108 of 360
1.2.24.6 Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D4
16
) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φ AD cycle
is achieved with 8-bit resolution and 33 φ AD with 10-bit resolution. Sample and hold can be selected
in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample
and hold is to be used.
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