Renesas M16C Series User Manual

Programming Notes
M30240 Group
Rev.1.00 Sep 24, 2003 Page 137 of 360
1.5.5 Programming Notes
1.5.5.1 Accessing USB IN/OUT Control and Status Registers
Do not use read-modify-write instruction on these registers because they contain control and status
bits that can be changed by both hardware and software. There is a possibility that using a read-mod-
ify-write instruction might cause incorrect data to be written back to these registers. See Table 1.52
for a list of bits that may have incorrect data written to them and the value you should write back in
order to prevent this from occurring.
The Endpoint 1-4 IN CSR’s (EPiICS, i = 1-4) have a bit IN_PKT_RDY (bit 0) that is set to a “1” by the
firmware after a packet of data is loaded to the respective endpoint’s FIFO. This signifies that a packet
is ready for transmission. If the firmware wants to send a NULL packet to the host, it can simply write
a “1” to the IN_PKT_RDY bit without loading data to the FIFO. This bit is cleared by the hardware. If
the firmware manipulates (writes) the IN CSR for a purpose other than to signify to the hardware that
a data packet is ready for transmission (for instance, set/reset ISO bit, set/reset SEND_STALL bit), it
must make sure that a “0” is written back to the IN_PKT_RDY bit. Failure to do so could cause improp-
er operation of the device. Writing a “0” to the IN_PKT_RDY bit has no effect on its state.
The Endpoint 1-4 OUT CSRs (EPiICS, i = 1-4) have a bit OUT_PKT_RDY (bit 0) that is set to a “1” by
the hardware after a packet of data is received from the host to the respective endpoint’s FIFO. This
signifies that a packet is ready for download. This bit is cleared by the firmware by writing a “0” to it
after the data packet is unloaded from the FIFO. If the firmware manipulates (writes) the OUT CSR for
a purpose other than to signify to the hardware that a data packet has been unloaded (for instance,
set/reset ISO bit, set/reset SEND_STALL bit), it must make sure that a “1” is written back to the
OUT_PKT_RDY bit. Failure to do so could cause improper operation. Writing a “1” to the
OUT_PKT_RDY bit has no effect on its state.
Table 1.52: Bits that might have incorrect data
Register name Bit name Value to write for “No change”
EP0CS
IN_PKT_RDY (b1) “0”
DATA_END (b3) “0”
FORCE_STALL (b4) “1”
EPxICS (x = 1-4)
IN_PKT_RDY (b0) “0”
UNDER_RUN (b1) “1”
EPxOCS (x = 1-4)
OUT_PKT_RDY (b0) “1”
OVER_RUN (b1) “1”
FORCE_STALL (b4) “1”
DATA-ERR (b5) “1”

Renesas M16C Series Specifications

General

Architecture	16-bit
Core	M16C
Instruction Set Architecture	CISC
Flash Memory	Up to 512 KB
Operating Voltage	2.7V to 5.5V
Operating Temperature Range	-40°C to +85°C
Package Types	LQFP, QFP
Timers	Multiple 16-bit timers
ADC	10-bit
Communication Interfaces	UART, SPI, I2C
Interrupts	Multiple interrupt sources

Summary

Chapter 1: Hardware

1.1 Description

Overview of the M30240 group as a single-chip USB peripheral microcontroller based on M16C family.

1.1.1 Features

Lists the key features of the M30240 group, including CPU, USB capabilities, memory, voltage, and peripherals.

1.1.3 Pin Configuration

Shows the pin configuration (top view) of the M30240 group, detailing each pin's name, I/O, and basic function.

1.1.4 Block Diagram

Presents a block diagram illustrating the internal structure and major components of the M30240 group.

1.1.5 Performance outline

Details the performance specifications of the M30240 group, including instruction count, memory capacity, and I/O ports.

1.1.6 Pin Description

Provides a detailed description of each pin of the M30240 microcontroller, including its name, I/O type, and functions.

CHAPTER 2: PERIPHERAL FUNCTIONS USAGE

2.1 Protect

Explains the protect function to prevent unintended changes to important registers when a program runs away.

2.2 Timer A

Provides an overview and detailed operation modes of the 16-bit Timer A, including timer, event counter, and PWM modes.

2.3 Timer B

Details the operation and registers of Timer B, a 16-bit timer that operates only in timer mode.

2.4 Clock-Synchronous Serial I/O

Explains clock-synchronous serial communication, including transmission/reception formats, transfer rates, and error detection.

2.5 Clock-Asynchronous Serial I/O (UART)

Covers UART operations, including transmission/reception formats, transfer rates, error detection, and functions like SIM interface compliance.

2.6 A-D Converter

Describes the A-D converter, its modes of operation, conversion clock, conversion time, and related registers.

2.7 DMAC

Explains the DMAC (Direct Memory Access Controller) for data transfer between memory and peripherals without CPU intervention.

2.10 Address Match Interrupt

Explains the address match interrupt functionality for simplified debugging, including enable/disable and timing.

2.11 Key-Input Interrupt

Describes the key-input interrupt, which is generated by falling edges on Port 0 or Port 1 pins used as input.

2.12 Power Control

Explains power control modes (Normal, Wait, Stop) for reducing CPU power consumption by stopping oscillators or clocks.

2.13 Programmable I/O Ports

Details the programmable I/O ports, including direction registers, port registers, pull-up control, and high drive capacity.

Chapter 3 Universal Serial Bus

3.1 Frequency Synthesizer

Explains how to set up and use the frequency synthesizer to generate the 48MHz clock for USB and DC-DC converter power.

3.2 Universal Serial Bus

Provides an overview of the Universal Serial Bus (USB) features, including specification compatibility, error handling, and transfer types.

3.2.2 USB Related Registers

Lists and describes USB-related registers for controlling USB functionality, including control, status, and enable registers.

3.2.7 USB Interrupts

Details the types of USB interrupts (Function, Reset, Resume, SOF, Suspend) and their handling via enable flags and priority levels.

3.2.8 USB Function Control Unit Initialization

Outlines the initialization routine for the USB Function Control Unit, including frequency synthesizer setup and endpoint initialization.

3.2.9 USB Control Transfers and SET_ADDRESS Request

Explains USB control transfers, the SET_ADDRESS request, and procedures for setting the device address.

Chapter 4 Interrupts

4.1 Overview of Interrupts

Provides an overview of interrupt types, including software, hardware, special, and peripheral I/O interrupts.

4.1.1 Type of Interrupts

Classifies interrupts into maskable and non-maskable types, detailing software and hardware interrupt categories.

4.1.2 Interrupt Vector Tables

Describes interrupt vector tables, including fixed and variable types, and lists interrupts assigned to fixed vector tables.

4.1.3 Interrupt Control

Explains interrupt control registers, interrupt request bits, enable flags, and priority levels for managing interrupts.

4.1.4 Interrupt Sequence

Details the sequence of operations when an interrupt occurs, including saving registers and processor control flow.

4.1.5 Multiple Interrupts

Explains how multiple interrupts are handled, including priority levels and interrupt acceptance conditions.

Chapter 5 Built-in PROM Version

5.1 Built-in PROM Version

Introduces the built-in PROM version, its functions, and available types (OTP and EPROM).

5.1.1 Outline

Outlines the capabilities of the built-in PROM version, including programming methods and suitability for different production volumes.

5.2 EPROM version

Describes the EPROM version, its operating modes (Normal, EPROM), and related pins.

5.2.1 EPROM mode pins

Lists pin functions specifically for the EPROM mode, detailing their roles in programming and verification.

5.2.2 Input/Output signals

Explains the input/output signals for Read, Program, and Erase operations in EPROM mode.

5.2.3 Algorithm Programming

Details the step-by-step algorithm for programming the built-in PROM, including voltage settings and pulse application.

5.3 Usage Precaution

Provides precautions for using built-in PROM versions, including handling of high voltage and protection of the EPROM window.

5.3.1 Built-in PROM versions

Offers specific cautions for programming built-in PROM versions, emphasizing voltage and power-on sequences.

5.3.2 One-time PROM versions

Highlights that OTP versions are not tested/screened, recommending programming and testing for reliability.

5.3.3 EPROM versions

Advises on protecting the EPROM window from light and cleaning it before erasure for optimal performance.

Chapter 6 Standard Characteristics

6.1 Standard DC Characteristics

Presents standard DC characteristics of the M30240EC, including output currents and voltage ratings.