Renesas M16C Series

Overview of Interrupts
M30240 Group
Rev.1.00 Sep 24, 2003 Page 339 of 360
4.1.3.5 IPL Variation
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values
shown in Table 4.6 is set in the IPL.
4.1.3.6 Interrupt Control Rewrite
Rewrite the interrupt control register only when it does not generate the interrupt request for that reg-
ister. If there is possibility of the interrupt request occurring, rewrite the interrupt control register after
the interrupt is disabled. The following describes some program examples:
When an instruction to rewrite the interrupt control register is executed and the interrupt is disabled,
the interrupt request bit is not always set even if the interrupt request for that register has been gen-
erated. This will depend on the instruction. If this creates problems, use the instructions below to
change the register.
Instructions: AND, OR, BCLR, BSET.
Table 4.6: Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels Value set in the IPL
Watchdog timer, NMI 7
Reset 0
Other Not changed
Example 1:
INT_SWITCH1:
FCLR I :Disable interrupts.
AND.B #00h, 0055h ;Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET I ;Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I :Disable interrupts.
AND.B #00h, 0055h ;Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ;Dummy read.
FSET I ;Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ;Push Flag register onto stack
FCLR I ;Diable interrupts.
AND.B #00h, 0055h ;Clear TA0IC int. priority level and int. request bit.‘
POPC FLG ;Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2, is to
prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to the
effects of the instruction queue.