Renesas M16C Series

Power Control
M30240 Group
Rev.1.00 Sep 24, 2003 Page 279 of 360
2.12.2 Stop Mode Set-Up
Settings and operation for entering stop mode are described here.
(1) Enable the interrupt that is to be used for returning from stop mode.
(2) Set the interrupt enable flag (I flag) to “1”.
(3) Clear the protection register
(4) Set all the clock stop bits to “1”.
Figure 2.128 shows the set-up of the stop mode.
Figure 2.128: Set-up for the Stop mode
b7 b0
(3) Canceling protect
Protect register [Address 000A 16]
PRCR
1
Enables writing to system clock control registers 0 and 1
(addresses 0006
16 and 000716)
1 : Write-enabled
All clocks off (stop mode)
(4) All clocks off (stop mode)
b7 b0
System clock control register [Address 0007 16]
CM1
0000
Reserved bit
Must be set to “0”
All clock stop control bit
1 : All clocks off (stop mode)
1
Interrupt control register
BCNIC [Address 004A16]
KUPIC [Address 004D
16]
SiTIC(i=0 to 2) [Address 0051
16, 005316, 004F16]
SiRIC(i=0 to 2) [Address 0052
16, 005416, 005016]
TAiIC(i=0 to 4) [Address 0055
16 to 005916]
TBiIC(i=0 to 1) [Address 005A
16 to 005B16]
SUSPIC [Address 0044
16]
RSMIC [Address 0046
16]
RSTIC [Address 005C
16]
USBFIC [Address 005F
16]
(1) Setting interrupt to cancel stop mode
Make sure that the interrupt priority
level of the interrupt which is used to
cancel the wait mode is higher than
the processor interrupt priority(IPL) of
the routine where the WAIT
instruction is executed.
Interrupt priority level select bit
b7 b0
SOFIC [Address 004716]
INTiIC (i=0 to 1) [Address 005D
16 to 005E16]
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority(IPL) of
the routine where the WAIT instruction is executed.
Interrupt priority level select bit
b7 b0
0
Reserved bit
Must be set to “0”
(2) Interrupt enable flag
(I
flag) “1”