Renesas M16C Series User Manual

Clock-Asynchronous Serial I/O
M30240 Group
Rev.1.00 Sep 24, 2003 Page 214 of 360
2.5.2.2 Reception in UART mode
For receiving data in UART mode, select functions from those listed in Table 2.21 . An example using
the indicated options is described below. Figure 2.65 shows the operation timing, and Figure 2.66 and
Figure 2.67 show the set-up procedures.
Table 2.21: Serial I/O reception in UART mode functions
Note 1: UART0, UART1 only
Note 2: UART2 only
Operation
(1) Setting the receive enable bit to “1” readies data-receivable status. At this time, output from the
RTSi
pin goes to “L” level to inform the transmission side that the receivable status is ready.
(2) When the first bit (the start bit) of reception data is received from the RxDi pin, output from the RTS
goes to “H” level. Then, data is received, bit by bit, in sequence: LSB to MSB, and stop bit(s).
(3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted to
the UARTi receive buffer register.
At this time, the receive complete flag goes to “1” to indicate that the reception is completed, the UARTi
receive interrupt request bit goes to “1”, and output from the RTS
pin goes to “L” level.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register is
read.
Item
Set-up Item Set-up
Transfer clock source
(Note 1)
Internal clock (f1/f8/f32)
Data logic select function
(Note 2)
O No reverse
O External clock (CLKi pin) Reverse
RTS
function
O RTS
function enabled
TxD, RxD I/O polarity
reverse bit (Note 2)
O No reverse
RTS
function disabled Reverse
Sleep mode (Note 1)
O Sleep mode off
Bus collision detection
function (Note 2)
O Not selected
Sleep mode on Selected

Renesas M16C Series Specifications

General

Brand	Renesas
Model	M16C Series
Category	Computer Hardware
Language	English