Renesas M16C Series User Manual

UART0 to UART2
M30240 Group
Rev.1.00 Sep 24, 2003 Page 96 of 360
1.2.23.3 Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding
some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this func-
tion. Table 1.29 shows the specifications of clock-asynchronous serial I/O mode (compliant with the
SIM interface). Figure 1.92 shows the typical transmit/receive timing in UART mode.
Note 1: ‘n’ denotes the value 00
16
to FF
16
that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Also, the UARTi receive interrupt request bit
is not set to “1”.
Table 1.29: Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item Specification
Transfer data
format
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 0378
16
= “101
2
”)
• One stop bit (bit 4 of address 0378
16
= “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 0378
16
= “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D
16
= “0”).
Set transfer format to LSB (bit 7 of address 037C
16
= “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 0378
16
= “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D
16
= “1”)
Set transfer format to MSB (bit 7 of address 037C
16
= “1”)
Transfer clock
• With the internal clock chosen (bit 3 of address 0378
16
= “0”): fi / 16 (n + 1) (Note 1): fi=f1, f8, f32
Transmission /
reception control
• Disable the CTS
and RTS function (bit 4 of address 037C
16
= “1”)
Other settings
• The sleep mode select function is not available for UART2
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D
16
= “1”)
Transmission start
condition
• To start transmission, the following requirements must be met:
Transmit enable bit (bit 0 of address 037D
16
) = “1”
Transmit buffer empty flag (bit 1 of address 037D
16
) = “0”
Reception start
condition
• To start reception, the following requirements must be met:
Reception enable bit (bit 2 of address 037D
16
) = “1”
Detection of a start bit
Interrupt request
generation timing
• When transmitting
When data transmission from the UART2 transfer register is completed (bit 4 of address 037D
16
= “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
On the reception side, an “L” level is output from the TxD2 pin by use of the parity error signal output
function (bit 7 of address 037D
16
= “1”) when a parity error is detected
On the transmission side, a parity error is detected by the level of input to the RxD2 pin when a
transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)

Renesas M16C Series Specifications

General

Brand	Renesas
Model	M16C Series
Category	Computer Hardware
Language	English