Universal Serial Bus
M30240 Group
Rev.1.00 Sep 24, 2003 Page 42 of 360
1.2.18.1.2 Generic Function Interface
The GFI handles all USB standard requests from the host through the control endpoint (endpoint zero), han-
dles Bulk, Isochronous and Interrupt transfers through Endpoints 1-4. The GFI handles read pointer reversal
for re-transmission the current data set; write pointer reversal for reception of the last data set again and data
toggle synchronization.
1.2.18.1.3 Serial Engine Interface Unit
The SIU block decodes the Address and Endpoint fields from the USB host.
1.2.18.1.4 Microcontroller Interface
The MCI block handles the Microcontroller interface and performs address decoding and synchronization of
control signals.
1.2.18.1.5 USB Transceiver
The USB transceiver, designed to interface with the physical layer of the USB, is compliant with the USB Spec-
ification (version 1.1) for full-speed devices. It consists of two 6-ohm drivers, a receiver, and Schmitt triggers
for single-ended receive signals.
The transceiver also includes a voltage converter. The voltage converter can supply 3.0 - 3.6V to the trans-
mitter when the rest of the chip (CPU, USB FCU) operates at 4.15 - 5.25V. To enable the voltage converter,
set bit 4 of the USB Control Register (USBC) to a “1”. To disable the voltage converter, set bit 4 of the USBC
to a “0”. Refer to Section 1.5.4 “USB Transceiver” for more detailed information.
Figure 1.29: USB Function Control Unit Block Diagram
1.2.18.2 USB Interrupts
There are five USB interrupts in this device:
• USB Function interrupt
• USB Reset interrupt
• USB Suspend interrupt
• USB Resume interrupt
• USB Start-of-Frame (SOF) interrupt.
The first four interrupts are used to control the data flow and USB power. The SOF interrupt is used
to monitor the transfer of isochronous (ISO) data. Each of the five USB interrupts is enabled by setting
the corresponding bit in the Interrupt Control Register of the Interrupt Control Unit. Because the USB
Function Interrupt has multiple interrupt sources, another level of enabling is within the USB Interrupt
Registers 1 & 2.
CPU
MCI
SIU
GFI
FIFOs
SIE
Transceiver
D
+
D
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