Renesas M16C Series User Manual

DMAC
M30240 Group
Rev.1.00 Sep 24, 2003 Page 261 of 360
2.7.2.2 Repeat transfer mode
In repeat transfer mode, an example of selected functions are shown in Table 2.38. Figure 2.105 shows
an example of operation and Figure 2.106 shows the set-up procedure.
Table 2.40: DMAC in repeated transfer mode functions
Operation
(1) When a software trigger is selected, setting the software DMA request bit to “1” generates a DMA
transfer request signal.
(2) If the DMAC is active, the data transfer starts and the contents of the address, indicated by the
DMAi forward-direction address pointer, are transferred to the address indicated by the DMAi destina-
tion pointer. When data transfer starts immediately after the DMAC becomes active, the value of the
DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the value of the
DMAi source pointer is reloaded by the DMAi forward-direction address pointer. Each time a DMA
transfer request signal is generated, 2 bytes of data are transferred. The DMAi transfer counter is dec-
remented, and the DMAi forward-direction address pointer is incremented.
(3) Though the DMAi transfer counter is underflowed, the DMA enable bit is still “1”. The DMA interrupt
request bit changes to “1” simultaneously.
(4) After the DMAi transfer counter is underflowed, when the next DMA request is generated, DMA
transfer is repeated from (1).
Figure 2.105: Operation of repeat transfer mode
Item
Set-up
Transfer space
From any SFR, ROM or RAM address to a fixed address
O From a fixed address to any ROM, RAM or SFR address
From one fixed address to another fixed address
Unit of transfer
8 bits
O 16 bits
Source
Source
Source
DMAi
request bit
DMA transfer
counter
DMAi
interrupt
request bit
DMAi
enable bit
• In the case in which the number of transfer times is set to 2.
Address bus
Data bus
“1”
Write signal to
software DMAi
request bit
Source
Indeterminate 0016
Dummy cycle
CPU use
CPU use
(3) Underflow
FF16
CPU use
Source
CPU use
Cleared to “0” when interrupt request is accepted, or cleared by software
CPU use
CPU use
0016
CPU use Source
CPU use
Destination
0116 0116
Destination Destination Dummy cycle
Destination
Dummy cycle
Destination
Dummy cycle
Dummy cycle
Destination
Dummy cycle
(1) Request signal for a DMA transfer occurs
(2) Data transfer begins
internal clock Φ

Renesas M16C Series Specifications

General

Brand	Renesas
Model	M16C Series
Category	Computer Hardware
Language	English