Power Control
M30240 Group
Rev.1.00 Sep 24, 2003 Page 281 of 360
2.12.4 Precautions
(1) The processor does not switch to stop mode when the NMI pin is at “L” level.
(2) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main
clock oscillation is stabilized.
(3) When switching to either wait mode or stop mode, instructions occupying four bytes after the WAIT
instruction or after the instruction that sets the all clock stop bit to “1” within the instruction queue are
pre-fetched when the program stops. So put at least four NOPs in succession after the WAIT instruction
or after the instruction that sets the all clock stop bit to “1”.
(4) Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each programmable I/O port even when it goes to wait mode or to
stop mode. A current flows in active I/O ports. A pass current flows in input ports that float. When en-
tering wait mode or stop mode, set non-used ports to input and stabilize the potential.
(b) A-D converter
A current always flows in the V
REF pin. When entering wait mode or stop mode, set the Vref connection
bit to “0” so that no current flows into the V
REF pin.
(c) Stopping peripheral functions
In wait mode, stop non-used wait peripheral functions using the peripheral function clock stop bit.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
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