Universal Serial Bus
M30240 Group
Rev.1.00 Sep 24, 2003 Page 309 of 360
3.2.2.19 USB Endpoint x(x = 0- 4) FIFO Register
This is the USB IN (transmission) FIFO and USB OUT (receive) FIFO data register. Data should be
written to this register at the time of transmission. Data should be read from this register at time of
receipt.
Figure 3.25 shows the structure of the USB Endpoint x(x = 0-4) FIFO Register.
Figure 3.25: USB Endpoint x FIFO Register
3.2.3 USB Transmit
Endpoints 0-4 have separate IN (transmit) FIFOs. The Endpoint IN FIFO structure is:
• Endpoint 0: 32 bytes
• Endpoint 1: 128 bytes
• Endpoint 2: 32 bytes
• Endpoint 3: 32 bytes
• Endpoint 4: 32 bytes
When Endpoint 0 is used:
The transmitted data are written to the IN FIFO, the IN_PKT_RDY bit should be set to “1”. The
IN_PKT_RDY bit automatically becomes “0” when the transmission of one data packet has been
completed or when the SETUP_END bit becomes “1”.
When Endpoints 1-4 are used:
If the AUTO_SET is “1”
• When data of equal size to the setting of the USB Endpoint x (x=1-4) IN MaxP register (0031B
16
,
00323
16
, 0032B
16
and 0333
16
) is written to the IN FIFO, the IN_PKT_RDY bit becomes “1” automat-
ically.
If the AUTO_SET is “0” or when a short packet less than the MaxP size is to be transmitted
• IN_PKT_RDY should be set to “1” with software after the transmission data is written to the IN FIFO.
The IN_PKT_RDY bit is cleared to “0” after the packet is successfully transmitted to the host.
When Endpoint 0 is used, the DATA_END bit should be set to “1” at the same time as the last data
packet is written to the IN FIFO. When DATA_END becomes “1”, the USB Function Control Unit
progresses to the next status phase. When the status phase completes, the FCU clears this bit to “0”.
The USB transmission default is a bulk transfer. Initialize each endpoint if another transfer mode is used.
Bit Symbol Bit Name
Function
R W
DATA0 to
DATA7
Endpoint x IN/OUT FIFO O O
Symbol
EPx (x=1-4)
Address
0338
16
, 0339
16
, 033A
16
, 03B4
16
, 03B4
16
When reset
00
16
USB Endpoint x FIFO Register
b7 b5b6 b4 b3 b2 b1 b0
FIFO data bits