Interrupts
M30240 Group
Rev.1.00 Sep 24, 2003 Page 32 of 360
1.2.12.2 Interrupt priority
The order of priority when two or more interrupts are generated simultaneously is determined by both
hardware and software.
The interrupt priority levels determined by hardware are Reset > NMI
> DBC > Watchdog timer > pe-
ripheral I/O interrupts > single-step > Address matching interrupt.
The interrupt priority levels determined by software are set in the interrupt control registers.
Figure 1.17 shows the circuit that judges the interrupt hardware priority level. When two or more inter-
rupts are generated simultaneously, the interrupt with the higher software priority is selected. Howev-
er, if the interrupts have the same software priority level, the interrupt is selected according to the
hardware priority set in the circuit.
The selected interrupt is accepted only when the priority level is higher than the processor interrupt
priority level (IPL) in the flag register (FLG) and the interrupt enable flag (I flag) is “1”. Note that the
reset, NMI
, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and unde-
fined instruction interrupts are accepted regardless of the interrupt enable flag (I flag).
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