Interrupts
M30240 Group
Rev.1.00 Sep 24, 2003 Page 33 of 360
Figure 1.17: Interrupt resolution circuit
USB Reset
Timer A4
Timer A2
USB SOF
UART1 reception
UART0 reception
UART2 reception
A-D conversion
DMA1
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission
Key input interrupt
DMA0
Processor interrupt priority level (IPL)
INT1
Timer B1
Level 0 (initial value)
Priority level of each interrupt
High
Low
Priority of peripheral I/O interrupts
(if priority levels are same)
Interrupt enable flag (I flag)
Watchdog timer
Reset
DBC
NMI
Interrupt
request
accepted
Address match
USB Suspend
USB Resume
USB Function
Timer A3
Timer A1
INT0
Timer B0
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